Non-volatile memory devices are widely used in many consumer, commercial and other applications. While some non-volatile memory devices, such as dynamic RAM and flash memory, use accumulated charge to store data, some other non-volatile memory devices, such as resistive random access memory (RRAM), phase change RAM (PRAM), and magnetic RAM (MRAM), use change in resistivity of a material therein to store data.
A resistive memory cell generally includes a first electrode, a second electrode, and a variable resistivity material connected therebetween. The resistive memory cell can be configured so that the resistivity of the material is controlled in response to a voltage that is applied between the first and second electrodes.
A PRAM device may include a phase changeable material layer which functions as a variable resistivity material. In response to sufficient heat, the phase changeable material layer may change phase so that its resistance changes and remains changed after its temperature returns to a pre-heating level. The phase changeable material layer may be formed from a chalcogenide material that includes germanium (Ge), antimony (Sb), and/or tellurium (Te). The phase of the material can be controlled in response to a level of current and/or duration of current that is applied to an electrode to heat the material a sufficient amount to change its phase. The resistance of the phase changeable material layer varies in response with its phase. For example, when the phase changeable material has a crystalline state, its resistance can be substantially less than when the phase changeable material layer has an amorphous state. Accordingly, the resistance of the phase changeable material in a PRAM device is controlled to store a logic value and is sensed to read the logic value.
FIGS. 1A-H are cross-sectional views illustrating a conventional method of manufacturing a phase changeable memory device. Referring to FIG. 1A, an electrical insulation layer 112 is formed on a substrate 100. The insulation layer 112 may be formed from, for example, silicon oxide and/or silicon nitride. A photo resist pattern is then formed on the insulation layer 112. The insulation layer 112 is patterned using the photo resist pattern as a mask to form an opening 117, with sidewalls 115, that exposes a portion of the substrate 100. The opening 117 may expose, for example, an impurity region in the substrate 100 that serves as a conductive line for the memory device.
A semiconductor member having first conductivity type impurities is formed to partially fill the opening 117. The semiconductor member is formed by a selective epitaxial growth (SEG) process using the exposed portion of the substrate 100 as a seed layer.
A vertical cell diode 145 is formed in the semiconductor member within the opening 117 by doping an upper region 146 thereof with second conductivity type impurity ions while a lower region 148 of the semiconductor memory has predominately first conductivity type impurity ions.
Referring to FIG. 1B, an ohmic layer 149 is formed within the opening 117 on the diode 145, such as by depositing a metal silicide through the opening 117 on an upper surface of the diode 145.
Referring to FIG. 1C, an insulating spacer layer 150 is formed on upper surfaces of the insulation layer 112, sidewalls 115 of the opening 117 above the ohmic layer 149, and on an upper surface of the ohmic layer 149. The spacer layer 150 is formed from silicon nitride at a temperature greater than 680° C. Referring to FIG. 1D, the spacer layer 150 is planarized to expose the upper surfaces of the insulation layer 112 and form insulating spacers 155 along sidewalls of the opening 117.
Referring to FIG. 1E, a metal layer 162 is formed on the spacers 155 along sidewalls of the opening 117 and on the ohmic layer 149. A metal nitride layer 164 is formed on the metal layer 162 in the opening 117. The metal layer 162 and the metal nitride layer 164 serve as a lower electrode layer 160.
Referring to FIG. 1F, an insulating filling member 170 is formed on the metal nitride layer 164 to fill a remaining portion of the opening 117. The filling member 170 may be formed at a temperature greater than 680° C. using, for example, an undoped silicate glass (USG) process, a spin-on-glass (SOG) process, a field oxide (FOX) process, a borophosphosilicate glass (BPSG) process, a phosphosilicate glass (PSG) process, a tetraethoxysilane (TEOS) process, a plasma-enhanced tetra ethyl ortho silicate (PE-TEOS) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, and/or a nitridation process to form silicon nitride.
Referring to FIG. 1G, the filling member 170 and the lower electrode layer 160 are planarized to expose upper surfaces of the insulation layer 112 and form a cup-shaped lower electrode 165 within the opening 117. The lower electrode 165 has the patterned metal layer 166 and the patterned metal nitride layer 168.
Referring to FIG. 1H, a phase changeable material layer is formed from a chalcogenide material on upper surfaces of the insulation layer 112, the filling member 170, and the lower electrode 165. A conductive upper electrode layer is formed on the phase changeable material layer. The phase changeable material layer and the upper electrode layer are patterned to form a phase change material pattern 180 and an upper electrode pattern 190, respectively.